1. Field of the Invention
The present invention relates to a junction field effect transistor.
2. Description of the Prior Art
Junction field effect transistors such as GaAs Schottky (barrier) gate field effect transistors, for, example, have a Schottky barrier formed on a gate region to control the flow of carriers by reversely biasing the Schottky barrier to change a width of a spatial electric charge region.
FIG. 1 of the accompanying drawings shows a conventional GaAs Schottky (barrier) gate field effect transistor. As shown in FIG. 1, two N-type high concentration regions (low resistance regions) 2 and 3 are formed on the surface of a semi-insulating GaAs substrate 1. An N-type low concentration region (channel region) 4 is formed between these low resistance regions 2 and 3. A P-type high concentration region 5 serving as a gate PN junction Ja is formed on the channel region 4. A drain electrode 6 and a source electrode 7 are respectively formed on the two low resistance regions 2 and 3 in an ohmic-contact fashion. A gate electrode 8 is formed on the P-type high concentration region 5 in a Schottky-contact fashion.
In the illustrated example, a ground potential Vss is applied to the source electrode 7 and a negative potential V.sub.G is applied to the source of the gate electrode 8 such that a PN junction Ja formed by the channel region 4 and the high concentration region 5 is reversely biased. A positive potential V.sub.D is applied to the drain electrode 6.
By the gate voltage V.sub.G applied to the gate electrode 8, the spatial electric charge region is downwardly widened from the gate. As a consequence, a passage (channel) of electrons flowing from the source to the drain is modulated by the depth of the spatial electric charge region and the drain current also is controlled by the gate voltage V.sub.G. An equivalent circuit of the Schottky gate field effect transistor is illustrated in FIG. 2 of the accompanying drawings.
It is customary that a cut-off frequency f.sub.T must be increased to increase the resistance ratio of the input and output in order to improve a high frequency characteristic of the Schottky gate field effect transistor. Accordingly, the characteristics of the junction field effect transistor are improved more if the gate length is shorter and a spacing between the gate and the source is narrower.
If the gate length is reduced, then an energy per unit area is increased, which lowers an electrostatic strength. Consequently, the transistor is considerably lowered in reliability and in service life.
The gate of a junction dual gate field effect transistor has the following problems.
As shown in FIG. 3 of the accompanying drawings, around a protecting diode 15 connected between a connection second gate connection electrode 19 and a source electrode 14, there are generated electric lines of force 18 which are directed from the second gate connection electrode 19 having a high potential to the source electrode 14 having a low potential.
The electric line of force 18 thus generated in the above direction exert a bad influence on the channel region beneath the gate electrode 16 within an active region 17, thereby cyclically changing a ratio of the change of a drain current versus the change of the first gate voltage, i.e., transconductance (hereinafter simply referred to as Gm).
The cyclic change of Gm makes the characteristic of a semiconductor apparatus 20 unstable and the semiconductor apparatus 20 cannot substantially achieve a desired amplification action.
Furthermore, study of the report reveals that, when a bias to the second gate is at a certain condition, a drain current (I.sub.D) and a drain conductance (gm) are vibrated at a frequency of 1 Hz to 1 kHz (see "Low Frequency Oscillation in GaAs IC's", Daniel Miller et al, GaAs IC Symposium-31, pp. 31-34, 1985).
A cause for this is not perfectly explained yet and is considered as follows: That is, if a leakage current is injected into the substrate from the source section of the field effect transistor (FET) or the electrode section of the drain or the electrode section of the gate, then this leakage current modulates the potential of the channel operation region/substrate interface of the FET. As a result, the drain current I.sub.D or drain conductance gm are vibrated at a low frequency.
In a dual gate field effect transistor in which a protecting diode for improving a withstand voltage property is formed on the second gate, it is frequently observed that the low frequency vibration of the drain current I.sub.D and the drain conductance gm takes place remarkably. A cause for this can be explained as follows. Generally, the dual gate FET is utilized in the state that the second gate is at a DC bias condition of 0 to 3 V. Therefore, if the second gate is positively biased strongly, then the leakage current, flowing into the substrate through the protecting diode provided on the second gate, is increased so that the drain current I.sub.D flowing through the channel operation region is modulated or the low frequency vibration of the drain conductance gm occurs.